Input buffer circuit

ABSTRACT

An input buffer circuit has a pass gate circuit coupled to an input. A pseudo-differential amplifier is coupled to the pass gate circuit. A level shifter is coupled to the pseudo-differential amplifier.

FIELD OF THE INVENTION

The present invention relates generally to the field of electroniccircuits and more particularly to an input buffer circuit.

BACKGROUND OF THE INVENTION

Semiconductor processing techniques are constantly improving and as theyimprove the required power supply voltages are reduced. The bestsemiconductor processing techniques today only require power supplyvoltages of around 1.8 volts. These processing techniques createtransistors commonly referred to as thin oxide transistors. Thin oxidetransistors are faster and can be used to produce denser circuits.Unfortunately, thin oxide circuits commonly have to interface with oldertechnology circuits that have high voltage power supplies (e.g., 2.5V,3.0V or 3.3V). These high voltage circuits contain transistors commonlyreferred to as thick oxide transistors. When it is necessary to converta signal from a high voltage to a low voltage, a buffer circuit isrequired. Prior art solutions use a buffer circuit that has both thickoxide transistors (components) and thin oxide transistors (components).As a result, the processing of these circuits is relatively complex andexpensive. Creating a buffer circuit with transistors that are all thinoxide transistors is difficult since the gate oxide voltage stress limitof the thin oxide transistors is lower than the high voltages beingapplied from an external source. Another problem is creating an inputbuffer circuit with thin oxide transistors that does not consume supplycurrent.

Thus there exists a need for an input buffer system that overcomes theseproblems.

SUMMARY OF INVENTION

An input buffer circuit includes a pass gate circuit coupled to aninput. A pseudo-differential amplifier is coupled to the pass gatecircuit. A level shifter is coupled to the pseudo-differentialamplifier. Note that a pseudo-differential amplifier as used hereinmeans a circuit that responds like a classical differential amplifierwhen the input voltage is in a range near a reference voltage on theother input, but that acts like a logic gate inverter when the inputvoltage is at a logic high or a logic low level. The reason for usingthe pseudo-differential amplifier is so the circuit does not consumesupply current when the input voltage is at a logic high or logic lowlevel. A classical differential amplifier would consume current underthose circumstances.

In one embodiment an inverter is coupled to an output of the levelshifter. In another embodiment, the pass gate circuit is formed withtransistors that are all the thin oxide type transistors. In anotherembodiment, the pass gate circuit has a bias input.

In one embodiment, the pseudo differential amplifier does not consumesupply current when an input to the pass gate circuit is at a high logiclevel. In another embodiment, the pseudo differential amplifier has acapacitor between a gate of a p-channel transistor and a gate of ann-channel transistor. In another embodiment, the pseudo differentialamplifier has an isolation transistor. In one embodiment, the inputbuffer circuit has a low threshold pass gate transistor. This may be anative transistor in one embodiment. A pseudo differential amplifier iscoupled to the low threshold pass gate transistor. In anotherembodiment, the pseudo differential amplifier is formed with devicesthat are all thin oxide devices. In another embodiment, the pseudodifferential amplifier has a first p-channel transistor and a secondp-channel transistor. The first p-channel transistor has a sourcecoupled to a low voltage supply and the second p-channel transistor hasa source coupled to a low voltage supply. In another embodiment, thepseudo differential amplifier has a first n-channel transistor that hasa drain coupled to a drain of the first p-channel transistor and asecond n-channel transistor that has a drain coupled to a drain of thesecond p-channel transistor. In yet another embodiment, the pseudodifferential amplifier has a third n-channel transistor that has asource coupled to a ground and a drain that is coupled to a source ofthe first n-channel transistor and to a source of the second n-channeltransistor. In one embodiment, a gate of the first p-channel transistorand a gate of the first n-channel transistor and a gate of the thirdn-channel transistor are coupled to an output of the low threshold passgate transistor.

In one embodiment, the pseudo differential amplifier does not consumesupply current when the input buffer is in a standby mode.

In one embodiment, the input buffer circuit has an input clippingcircuit. A pseudo differential amplifier is coupled to the inputclipping circuit. An inverter is coupled to the pseudo differentialamplifier. In one embodiment, the input buffer circuit includes a levelshifter coupled between the pseudo differential amplifier and theinverter.

In one embodiment, the input clipping circuit only has thin oxidetransistors. In another embodiment, the input clipping circuit has ap-channel pass gate transistor and an n-channel pass gate transistor. Inanother embodiment, the input clipping circuit has a p-bias input and ann-bias input.

In one embodiment, the pseudo differential amplifier has an isolationtransistor.

BRIEF DESCRIPTION OF THE DRAWING.

FIG. 1 is a block diagram of an input buffer circuit in accordance withone embodiment of the invention;

FIG. 2 is a circuit diagram of an input buffer circuit in accordancewith one embodiment of the invention;

FIG. 3 is a circuit diagram of an input buffer circuit in accordancewith one embodiment of the invention;

FIG. 4 is a graph of the operation of an input buffer circuit of FIG. 2in accordance with one embodiment of the invention; and

FIG. 5 is a graph of the operation of an input buffer circuit of FIG. 3in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an input buffer circuit 10 in accordancewith one embodiment of the invention. The circuit 10 includes an inputclipping circuit 12 coupled to an input signal (Vin) 14. Apseudo-differential amplifier 16 is coupled to the input clippingcircuit 12 and a reference voltage input (Vrep) 17. Note that apseudo-differential amplifier as used herein means a circuit thatresponds like a classical differential amplifier when the input voltageis in a range near a reference voltage on the other input, but that actslike a logic gate inverter when the input voltage is at a logic high ora logic low level. The reason for using the pseudo-differentialamplifier is so the circuit does not consume supply current when theinput voltage is at a logic high or a logic low level. A classicaldifferential amplifier would consume current under those circumstances.The pseudo-differential amplifier 16 is coupled to an inverter 18. Theinverter 18 has an output 20.

FIG. 2 is a circuit diagram of an input buffer circuit 30 in accordancewith one embodiment of the invention. The circuit 30 is similar to thecircuit 10 of FIG. 1. The circuit 30 has four major components: an inputclipping circuit 32 or pass gate circuit; a pseudo-differentialamplifier circuit 34; a level shifter 36; and an inverter 38. The inputclipping circuit 32 has an input 40 coupled to a source 42 of a firstp-channel transistor (P1) 44 and a drain 46 of a first n-channeltransistor (N1) 48. A gate 50 of the p-channel transistor 44 is coupledto a p-channel bias signal (PBIAS) 52. A gate 54 of the n-channeltransistor 48 is coupled to a n-channel bias signal (NBIAS) 56. Thedrain 58 of transistor 44 is coupled to an input (INP) 60 of thepseudo-differential amplifier circuit 34. The source 62 of transistor 48is coupled to an input (INN) 64 of the pseudo-differential amplifiercircuit 34. A capacitor (C1) 66 is coupled between the inputs INP 60 andINN 64, in one embodiment.

The input to the pseudo-differential amplifier 34 includes a referencevoltage input 68 and a second input formed by INP 60 and INN 64. Thesecond input is split into two separate inputs to protect the thin oxidetransistors. The p-channel input INP 60 is coupled to a gate 70 of asecond p-channel transistor (P2) 72 and a gate 74 of a sixth p-channeltransistor (P6) 76. The input INP 60 is also coupled to a drain 78 of azero p-channel transistor (P0) 80. The gate 82 and the source 84 oftransistor 80 are coupled to a high voltage power supply VEXT 86. Thesource 88 of transistor 72 and the source 90 of transistor 76 arecoupled to VEXT 86. The n-channel input INN 64 is coupled to the gate 92of the second n-channel transistor (N2) 94, the gate 96 of the eighthn-channel transistor (N8) 98 and to the drain 100 of the zero n-channeltransistor (N0) 102. The source 104 of transistor 94 is coupled to thedrain 106 of transistor 98. The source 108 of transistor 98 is coupledto ground VGND 110. The gate 112 and the source 114 of transistor 102are coupled to VGND 110. The input VREF 68 is coupled to the gate 116 ofthe seventh n-channel transistor (N7) 118. The source 120 of transistor118 is coupled to the drain 106 of transistor 98.

The pseudo-differential amplifier 34 requires a plurality of isolationtransistors to avoid exceeding the gate oxide limit of any of the thinoxide transistors used to form the pseudo-differential amplifier 34. Theisolation transistors are the third p-channel transistor (P3) 122, theseventh p-channel transistor (P7) 124, the third n-channel transistor(N3) 126 and the sixth n-channel transistor (N6) 128. The gate 130 oftransistor 122 and the gate 132 of transistor 124 are coupled to thePBIAS signal 52. The gate 134 of transistor 126 and the gate 136 oftransistor 128 are coupled to the NBIAS signal 56. The source 138 oftransistor 122 is coupled to the drain 140 of transistor 72. The drain142 of transistor 122 is coupled to the drain 144 of transistor 126. Thesource 146 of transistor 126 is coupled to the drain 148 of transistor94. The source 150 of transistor 124 is coupled to the drain 152 oftransistor 76. The drain 154 of transistor 124 is coupled to the drain156 of transistor 128. The source 158 of transistor 128 is coupled tothe drain 160 of transistor 118.

The output 162 of the pseudo-differential amplifier circuit 34 iscoupled to the drain 148 of transistor 94 and the source 146 oftransistor 126. The output 162 is coupled to the level shifter 36. Agate 164 of the fifth n-channel transistor (N5) 166 of the level shifter36 is coupled to the output 162. The input INN 64 is coupled to the gate168 of the fourth n-channel transistor (N4) 170. The source 172 oftransistor 170 and the source 174 of transistor 166 are coupled to VGND110. The drains 176, 178 of transistors 170, 166 are coupled to a pairof p-channel cross coupled transistors (P4, P5) 180, 182. The gate 184of transistor 180 is coupled to the drain 186 of transistor 182. Thegate 188 of transistor 182 is coupled to the drain 190 of transistor180. The sources 192, 194 of transistors 180, 182 are coupled to a lowvoltage power supply (VINT) 196. The input 198 of inverter 38 is coupledto the drain 190 of transistor 180. The output 200 forms the output ofthe circuit 30.

The input 40 is coupled to two pass transistors (P1, N1) 44, 48. Whenthe input 40 is high (VEXT) the output INP 60 is going to be VEXT andthe output INN 64 is going to be NBIAS less a Vtnl (n-channel thresholdN1). The transistor 72 coupled to the input INP 60 will turn off. Thetransistor 94 and transistor 98 are coupled to input INN 64 and are on.This couples the output 162 to VGND 110. As a result the output 162 ofthe pseudo-differential amplifier is low. The output 162 is coupled totransistor 166 of the level shifter 36. Since the output 162 is low, thetransistor 166 is off. Transistor 170 of the level shifter 36 is coupledto the input INN 64, which is high. As a result, transistor 170 is onand couples the input 198 of the inverter 38 to VGND 110, which resultsin the output 200 of the circuit 30 to be high.

When the input 40 is low (VGND) the output INP 60 is going to be PBIASplus a |Vtp1| (p-channel threshold P1) and the output INN 64 is going tobe VGND 110. The transistor 94 will be off since it is coupled to inputINN 64. The transistors 72 and 76 will be on since JNP is low.Transistor 122 will be on and therefor the drain 144 of transistor 126will see a voltage of VEXT. The source 146 of transistor 126 will pullup to approximately the voltage of NBIAS-Vtn3, since the transistor 94is off. The output 162 of the pseudo-differential amplifier 34 will thenbe approximately NBIAS-Vtn3, which will turn on transistor 166.Transistor 166 couples VGND 110 to the gate 184 of transistor 180,turning on transistor 180. Transistor 180 then couples the input 198 toVINT 196 or a high. As will be apparent to those skilled in the art thecircuit does not consume current when the input 40 is at a logic high orlogic low level. For a logic high input, transistors 72 & 76 are off sono current is consumed by the pseudo-differential amplifier 34. Thetransistors 166 and 180 are off in the level shifter 36, so no currentis consumed by the level shifter. For a logic low input, transistor 98is off so no current is consumed by the pseudo-differential amplifier34. The transistor 170 and 182 are off in the level shifter 36, so nocurrent is consumed by the level shifter.

The circuit 30 also needs to protect the gate oxides of the thin oxidetransistors while having a trip point in the specified region. In orderfor the circuit to work, the NBIAS input 56 must have a voltage greaterthan 2Vtn (n-channel threshold) plus V_(gsn2) (VNBIAS>2*Vtn+V_(gsn2)),where V_(gsn2) is the gate overdrive of transistor (N2) 94. In order toprotect the gate oxide of the n-channel transistors, NBIAS 56 must havea voltage that is less than the gate oxide stress limit. Similarly forthe circuit to work, the PBIAS input 52 must have a voltage less thanVEXT (high voltage power supply) less |2Vtp| (p-channel threshold) less|V_(gsp2)| (VPBIAS<VEXT−|2*Vtp|−|V_(gsp2)|), where V_(gsp2) is the gateoverdrive of transistor (P2) 72. In order to protect the gate oxide ofthe p-channel transistors, PBIAS 52 must have a voltage greater thanVEXT less the gate oxide stress limit.

The above description defines the required ranges for the bias voltagesto ensure both functionality and oxide protection. However, depending onthe external supply voltage VEXT and the threshold voltages Vtn and Vtp,an input dead zone region may exist. The input dead zone region 220 (seeFIG. 4) is defined as an input voltage region where both the internalinput INN 64 and INP 60 do not change. The trip point region 222 (seeFIG. 4) of the circuit must be outside the dead zone region 220 butabove the Vil 224 specification. The trip point region is shifted aboveVil 224 by the transistors 76, 124, 128, 118 and 98. As the input 40rises from 0V to Vtn the n-channel transistors 94 and 98 remain cut-offand the output 162 remains high. As the input 40 rises above a Vtn thetransistors 94 and 98 begin to conduct. For this conduction thetransistor 98 must sink current from both legs. This forces the drain106 to increase in voltage and reduces the gate to source voltage oftransistor 94. This action requires the input voltage to be higherbefore the output 162 will change state. As a result, the circuit trippoint is raised. The minimum trip point voltage is raised, which givesmore margin to the Vil 224 specification.

The capacitor 66 is included to reduce the skew in the outputtransitions. The propagation delay through the input buffer will bedifferent depending on the input transition. The capacitor 66 reducesthis skew by coupling the two internal inputs (INN,INP) together duringa transition. This acts to remove the dead zone region during transientoperation. The size of the capacitor needs to selected carefully, sincetoo much coupling could cause the transistors' oxides to be overstressed.

Transistors 102 and 80 are included to prevent the internal nodes INN 64and INP 60 from floating too low or high and over stressing thetransistor oxides.

The circuit 30 protects the thin oxide devices and provides a desirabletrip point. In addition, the circuit 30 does not consume supply currentwhen the input is near the rails (standby mode). This makes the circuitdesirable for portable applications.

FIG. 3 is a circuit diagram of an input buffer circuit 250 in accordancewith one embodiment of the invention. The difference between the circuit30 of FIG. 2 and the circuit 250 of FIG. 3 is that a low threshold ornative transistor is available. A native transistor (NN2) 252 performsthe function of the input clipping circuit 254. An input signal 256 iscoupled to a drain 258 of the pass gate transistor 252. A bias signal(NBIAS) 260 is coupled to the gate 262 of the is transistor 252. Thesource 264 is coupled to the input INI 266 of the pseudo-differentialamplifier 268. The pseudo-differential amplifier 268 has a firstp-channel transistor (P1) 270 with its gate 272 coupled to the input INI266. A gate 274 of a first n-channel (N1) transistor 276 and a gate 278of a second p-channel transistor 280 are coupled to the input INI 266also. The source 282 of transistor 270 and the source 284 of transistor280 are coupled to the internal or low voltage power supply VINT 286.The drain 288 of transistor 270 is coupled to the drain 290 oftransistor 276 and the input 292 of inverter 294. The source 296 oftransistor 276 is coupled to the drain 298 of a third n-channeltransistor (N3) 300 and to the source 302 of a second n-channeltransistor (N2) 304. The source 306 of transistor 300 is coupled toground VGND 308. The gate 310 of transistor 300 is coupled to the inputINI 266. The gate 312 of transistor 304 is coupled to the input VREF314. The drain 316 of transistor 304 is coupled to the drain 318 oftransistor 280. The output 320 of the inverter 294 is the output of thecircuit 250.

When the input signal 256, a high voltage signal, is high the pass gate252 clips the signal to a voltage equal to the voltage of the NBIASsignal 260. In one embodiment, the NBIAS signal 260 is equal to the VINTvoltage 286. As a result, the input INI 266 has a high logic level, VINTin one embodiment, this turns off transistor 270 and transistor 280.Transistor 276 is turned on, as is transistor 300. As a result theoutput 292 is coupled to VGND 308. Since the input 292 to inverter 294is low, the output 320 of the inverter is high. When the input signal256 is low, the source 264 of transistor 252 is low. This turns offtransistor 276 and the transistor 300. This turns on transistor 270 andtransistor 280. As a result, the input 292 of inverter 294 is coupled toVINT 286, a logic high. The output 320 of inverter 294 is a logic low.Note that transistor 300 prevents any current from flowing when theinput 256 is low and the transistors 270 and 280 prevent any currentfrom flowing when the input 256 is high. Thus, the pseudo-differentialamplifier does not consume current in standby mode (input 256 logic highor logic low).

The native transistor 252, which may be a low threshold transistor,clips the input voltage to provide gate oxide protection for thetransistors in the pseudo-differential amplifier 268. This allows thepseudo-differential amplifier 268 to be powered by the low voltage powersupply and to use transistors that are the thin oxide type transistors.The intent of transistors 280, 304, and 300 is to force the drain 298 oftransistor 300 high as the input voltage is raised from a low voltage toa high voltage. As the input rises from 0V to Vtn, the n-channel devices276 and 300 remain cut-off and the output 320 remains low. As the inputrises above a Vtn, the transistors 276 and 300 begin to conduct. Forthis condition, the transistor 300 must sink current from both legs ofthe pseudo-differential amplifier 268. This forces the drain 298 oftransistor 300 to increase in voltage and reduces the gate to sourcevoltage of transistor 276. As a result, the input voltage 256 must behigher before the output will change state. This effectively increasesthe trip point region 320 (see FIG. 5) of the circuit 250. This raisesthe trip point voltage, which gives more margin to the Vil specification321. Also, the inclusion of the second leg, including 280 and 304, andthe reference voltage input 314 gives more control on the maximum inputhigh trip point voltage. Thus, the circuit increases the noise margin tothe Vil specification 321 and tightens the trip point region. FIG. 5shows that the trip point region 320 includes a section above then-channel threshold Vtn 322. This occurs since the transistor 276remains in weak inversion for input voltages above a Vtn due to theaction of transistor 300. The circuit results in increasing the weakinversion region for the p and n channel transistors and the trip pointoccurs in this region.

The circuit 250 protects the thin oxides devices and provides adesirable trip point. In addition, the circuit 250 does not consumecurrent when the input is near the power supply Vint 286 or the groundsupply VGND 308 (standby mode). This makes the circuit desirable forportable applications.

While the invention has been described in conjunction with specificembodiments thereof, it is evident that many alterations, modifications,and variations will be apparent to those skilled in the art in light ofthe foregoing description. Accordingly, it is intended to embrace allsuch alterations, modifications, and variations in the appended claims.

What is claimed is:
 1. An input buffer circuit, comprising: a pass gatecircuit coupled to an input; a pseudo-differential amplifier coupled tothe pass gate circuit wherein the pseudo differential amplifier includesa capacitor coupled between a gate of a p-channel transistor and a gateof an n-channel transistor and wherein the pseudo differential amplifierdoes not consume supply current when the input to the pass gate circuitis at a high logic level; and a level shifter coupled to thepseudo-differential amplifier.
 2. The circuit of claim 1, furtherincluding an inverter coupled to an output of the level shifter.
 3. Thecircuit of claim 1, wherein the pass gate circuit includes transistorsthat are all low voltage type transistors.
 4. The circuit of claim 3,wherein the pass gate circuit has a bias input.
 5. The circuit of claim1, wherein the pseudo differential amplifier has an isolationtransistor.
 6. An input buffer circuit, comprising: a native pass gatetransistor; and a pseudo differential amplifier coupled to the nativepass gate transistor wherein the pseudo differential amplifier has afirst p-channel transistor and a second n-channel transistor the firstp-channel transistor having a source to a low voltage supply and thesecond p-channel transistors having a source coupled to the low voltagesupply, a first n-channel transistor having a drain coupled to a drainof the first p-channel transistor and a second n-channel transistorhaving a drain coupled to a drain of the second p-channel transistor, athird n-channel transistor having a source coupled to a ground and adrain coupled to a source of the first n-channel transistor and to asource of the second n-channel transistor, where a gate of the firstp-channel transistor and a gate of the first n-channel transistor and agate of the third n-channel transistor are coupled to an output of thenative pass gate transistor, wherein all the transistors forming thepseudo differential amplifier are low voltage type transistors.
 7. Thecircuit of claim 6, wherein the pseudo differential amplifier does notconsume supply current when the input buffer is in a standby mode.
 8. Aninput buffer circuit, comprising: an input clipping circuit wherein theinput clipping circuit includes transistors that are all thin oxide typetransistors and has a p-channel pass gate transistor and an n-channelpass gate transistor; a pseudo differential amplifier coupled to theinput clipping circuit; and an inverter coupled to the pseudodifferential amplifier.
 9. The circuit of claim 8, further including alevel shifter coupled between the pseudo differential amplifier and theinverter.
 10. The circuit of claim 9, wherein the input clipping circuithas a p-bias input and an n-bias input.
 11. The circuit of claim 8,wherein the pseudo differential amplifier has an isolation transistor.